We found out, that there is a serious
deficiency on all recent processors, which hinders significantly the
read, search and transfer rates.
In simple terms, there is a time penalty imposed by Pentium's read buffer.
Specifically, when while a burst is in progress, a read request is made in the same cache line (on the same burst) the processor halts until the burst has finished (documented) AND the penalty time expires! (undocumented).
We should point out, that this affects all normal read, search and transfer loops.
Andy Grove (Intel's CEO) commenting on Klamath's (now Pentium
II) double bus:
"It is not enough to deliver faster CPUs," Grove said. "We must deal with and cross the bandwidth valleys of death," meaning bottlenecks in the processor-to-memory and processor-to-graphics bus.
After a lot of experimentation and many measurements we found the
best workaround: By carefully redirecting the order of which memory reads
are made we increased the main memory read rate by about 71%
and the secondary cache read rate by 51%.
Measured on an Intel Pentium-200 MMX with Intel's HX chipset (TX has slight differences) and EDO memory. (SDRAM has increased main memory read and transfer rates).
The 'normal' rate is the rate
which is achieved with the best
normal way possible.
The 'innovative' rate is achieved by knowing the above mentioned read buffer flaw.
The source of this chart is Membench. For more information click on the chart.
(The innovative write rates on the chart are achieved using 64 bit writes, a method documented by Intel in its 1997 Optimizations manual; the 'performance flaw' revealed in this site is a read buffer flaw)
Don't know what a burst is? Proceed to schematic demonstration of the read buffer flaw.
For questions, go to the Q&A page.
For comments or suggestions, mail us
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